GDP-AI for Silicon and IP Lifecycle Management
Complete IP lifecycle management. Silicon lifecycle design data backbone.
IC Manage GDP-AI delivers complete IP lifecycle management by tying every IP instance and version directly into the live design database, enhanced by AI-driven IP packaging, IP support, and IP discovery. Throughout the entire lifecycle, IP can be managed and tracked, with status, defects, ECOs, and approvals all traceable and auditable wherever that IP is used — and fixes can be systematically propagated across all affected designs.
Because GDP-AI manages the full design database, its derivatives, and all IP instances under consistent version control and traceability, it extends beyond traditional IP lifecycle management to act as the design/IP data backbone for silicon lifecycle management (SLM) — providing the accurate, configuration‑aware source of truth as to what was actually designed and shipped that silicon digital twins, manufacturing analytics, and in‑field telemetry systems need to make lifecycle decisions.
Enterprise IP lifecycle management
Scalable IP reuse
GDP-AI’s lifecycle management scales to 100M+ IP components and 1000s of users. IP can be captured from third‑party sources and all commercial design data management systems and Git — eliminating disruptive data migration and preserving existing engineering investments, regardless of where it was created.
AI-driven IP lifecycle management
IC Manage GDP AI provides end to end, scalable hierarchical IP lifecycle management across the enterprise through all IP stages, supporting consistent governance and compliant design flows, and leveraging AI-driven IP packaging, IP support, and IP discovery workflows to increase IP reuse with dramatically reduced manual effort.
- IP capture and qualification. GDP-AI’s embedded AI replaces the extensive manual effort for developers to package their IP and metadata (such as bugs, assertions, constraints, and key electrical and simulation parameters) according to each company’s IP publishing standards. IP developers can instead point GDP-AI to their workspace and GDP-AI interprets the disparate formats (spreadsheets, PDFs, bug trackers…), extracts the necessary data, and packages it for IP developer approval for automatic publishing to the central IP catalog.
- IP publishing. The IP owner reviews and approves the AI-generated package for automatic publishing to the company’s centralized IP catalog, enabling enterprise-wide, controlled visibility and access, including any licensing information and restrictions.
- IP discovery and reuse. IP consumers use conversational queries for IP discovery. GDP-AI interprets intent and returns the best-suited IP and configurations for the designer to assess. Custom datasheets are dynamically rendered, including links to external systems such as documentation management and bug tracking.
- Lifecycle traceability and governance. Across all stages, semiconductor IP owners and management have fine‑grained traceability of each IP instance and its usage across the IP and full design hierarchy, enabling consistent IP governance and simplifying compliance reporting and audits.
- IP change management and evolution. Change requests, updates, and issue tracking are managed through integrated workflows, leveraging AI-driven IP support to resolve semantic documentation inquiries and ensure only actual bugs are escalated to developers. Workflows include Jira links to track IP changes, with automatic notifications to relevant project teams when IP is updated, impacted, or fixed.
- IP retirement. IP that is no longer in use can be retired, with its lifecycle state changed as appropriate (e.g., deprecated, read-only, or no longer supported), ensuring obsolete IP cannot be introduced into new designs while preserving full historical context.
Centralized, Searchable IP Catalog
Search and discovery
AI-driven IP discovery
IP consumers use conversational queries to discover IP best suited for their needs from the central IP catalog. GDP-AI interprets intent, then queries the IP catalog and the live GDP-AI database to return precise information about IP configurations, versions, properties, and recent changes.
Google-like search and filtering
A general-purpose web UI-based search enables keyword searching across the entire IP catalog. Designers can also filter by IP classification (such as analog, digital, etc.) and specific properties such as technology node.
Portfolio-level visibility & reporting
GDP-AI provides real-time visibility into IP status, usage, and readiness across projects, enabling teams to track IP progress throughout the IP lifecycle management process, while the system enforces the programmable workflow rules. Customizable dashboards in Envision provide interactive, tailored views and reporting across IP, projects, and configurations.
Configuration-aware search and analytics
Configuration‑aware IP search and configuration datasheets give teams precise visibility into IP content across every level of the IP and design hierarchy, including inherited metadata such as status and usage across the hierarchy. Configuration analytics are available through Envision.
Enterprise context & traceability
End-to-end IP traceability.
GDP-AI provides centralized IP and metadata tracking across projects, with traceability spanning the full program record — requirements, third-party IP licensing obligations, verification and regression results, pre-tapeout bugs, and post-silicon bugs across all design derivatives.
Links to external systems
HTML links to documentation systems or verification trackers can be embedded so engineers have a single IP window that pulls in all relevant information in one place.
Live data access to PLM & identity management systems
IP catalog search results are always up to date, reflecting changing information in other systems. GDP-AI provides workflow automation and API integrations for updating metadata fields from external PLM and tapeout systems frequently throughout the day.
Extensibility and security
Web API
Programmatic access enables custom integrations for IP lifecycle management and automation pipelines across the enterprise tool chain.
Team-fencing for IP protection
Team-fencing prevents IP leakage by restricting access based on the user’s team (e.g. a team in a certain region) — acting as an invisible fence around digital design assets, ensuring sensitive data cannot be accessed from or exported to unauthorized teams, even by users with valid credentials.
Unified hierarchical BOM management
IC Manage GDP‑AI enables engineers to assign domain specific Bills of Materials (BOMs) for software, drivers, CAD tools, EDA tools, RTL, and analog design to each project configuration, dynamically leveraging and refining existing design content within a unified hierarchical IP and project structure, effectively serving as a Bill of Information (BOI) for each configuration.
Engineers can also build planning BOMs for early build-or-buy analysis using a shopping‑cart style flow, with “in‑progress” states and flags controlled by the same programmable finite state machine that governs formal releases.
IC Manage then assembles these domain level BOMs into a scalable, high‑performance, hierarchical project BOM and configuration that provides an authoritative record of the SoC state at every milestone, serving as the system‑level Bill of Information (BOI), tracking the component versions and dependency relationships needed for comprehensive bidirectional traceability across the full IP hierarchy.
Domain BOMs and configurations can be instantly cloned and adapted for new projects, ensuring teams start from verified, silicon proven setups instead of rebuilding BOMs from scratch.
This unified architecture provides up to date visibility into both individual and project level BOMs in one place, allowing teams to programmatically confirm that any change maintains configuration integrity and end-to-end data continuity before the configuration is shared or released.
AI insights and automation
AI-enhanced data access and automation
Natural language queries, automated script generation, workflow automation, live project insights, and semantic access to deep technical knowledge boost designer efficiency and shorten the time to error-free tapeouts.
Workflow automation and extensible scripting
Engineers can inject scripts and triggers for pre- and post-workspace operations, and automate end-to-end processes, such as running a simulation, pulling test results, and pushing updates to datasheets via a command line interface.
Automated workspace creation and population
Advanced caching and high‑bandwidth distributed data infrastructure, combined with rule‑driven filtering and validation, enable consistent workspace creation at global enterprise scale.
Lifecycle governance and traceability
Complete revision control
GDP‑AI maintains exhaustive revision control of all database states, versioning every incremental change made across projects, workspaces, and configurations from initial creation through tapeout, providing the foundation for IP governance.
Automated hierarchical release management
Release processes are automated with full awareness of complex cross‑domain dependencies and the underlying IP hierarchy, ensuring nothing is released out of sequence or with missing components, and that only fully qualified configurations are promoted to tapeout.
Comprehensive IP audit trail
GDP‑AI stores the complete temporal history of each IP’s state progression and metadata changes. Engineers and managers can generate a full, audit‑ready report at any time, supporting lifecycle governance and enabling audit‑ready compliance.
Secure, enterprise-scale platform
EDA flow integrations
GDP‑AI integrates directly with Cadence and Synopsys design environments, enabling IP, configurations, and workspaces to be managed within native design flows.
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Storage and disk space optimization
GDP-AI leverages NFS library shares and data-deduplication to enable disk sharing, significantly reducing disk space consumption.
Phishing-resistant SSO and access control
Integrated OKTA‑based single sign‑on centralizes access, streamlines engineer workflows with one login, enforces phishing‑resistant MFA, and automates onboarding and offboarding — ensuring IP protection and supporting enterprise compliance requirements.
IC Manage: The industry leader in semiconductor IP management
IC Manage defined the IP management category more than a decade ago and was highlighted by John Cooley at DAC as the ‘#1 must-see tool.’ Today, IC Manage continues to lead in high‑performance IP management — including IP lifecycle management.
Customers include Altera, AMD, Apple, Infineon, Microchip, NVIDIA, Qualcomm, Samsung, Viasat, and dozens of other top semiconductor and systems companies.
NXP | Udi Landen
“IP reuse is inherently difficult due to competing demands on IP developers’ time, the variety of historic designs, and the quantity of different methodologies involved.
“With IC Manage, we were able to deliver a global IP Catalog as a key part of NXP’s strategy to fully leverage the value of our IP.”
Biotronik | David Genzer
“Biotronik uses GDP design and IP management for maintaining revisions and tracking of internal IP reuse in multiple types of medical implantable products.
“Internally, GDP manages multi-site reliable tracking of massive IC databases, ultra low power IP Libraries, design test benches, and project tracking info for many highly successful tapeout of IC’s.”
DeepChip | John Cooley
“It came as no surprise to me that IP Central made the DAC Top 5 ‘hot’ tools with chip designers
“There is a high demand for something that can take 100’s or 1000’s of internally developed IP and make them reusable across your company.
“It’s a real headache that IP Central is curing.”
DeepChip Survey| Anonymous Semiconductor user
“For the first time we can mix foreign depots/revision control system (such as DesignSync, ClearCase, Subversion, Perforce) in IC Manage and sync them… This multi-repository configuration management is good for IP reuse. The IP/design module has a path and a history inside the depot, rather than being checked in as a new object.”
What is IP Lifecyle Management?
IP lifecycle management involves managing how semiconductor IP blocks are created, reused, and retired across many designs, ensuring that every IP version, its verification and bug history, and every place it is instantiated in chips and subsystems is tracked and governed.
