Technical Papers

Whitepaper: IC Manage PeerCache EDA Tool Accelerator

IC Manage’s CEO Dean Drako presents at Design Automation Conference 2014 on potential applications and impact for big data in SoC and IC design. Covers basic steps development teams can take today to prepare for Big Data analytics in future years.

Dean Drako on Big Data at DAC 2014

IC Manage’s CEO Dean Drako presents at Design Automation Conference 2014 on potential applications and impact for big data in SoC and IC design. Covers basic steps development teams can take today to prepare for Big Data analytics in future years.

Multi-site Design and IP Management Survey Report 2014

This is the sixth annual survey report related to Design & IP Management. It is based on an independent worldwide survey executed during Spring of 2014. A total of 361 engineering professionals responded, with approximately half in management roles. This report focuses closely on multi-site design and IP management for both digital and custom/analog design. The report’s scope spans: organization policy on IP Reuse modification; IP reuse internal drivers, multi-site design and IP management priorities, and security issues.

IC Manage Dean Drako on IP & Design Data Management Metrics

Below is a collection of articles on Deepchip.com written by Dean Drako, IC Manage’s President and CEO. According to Drako: “If I had to characterize this year’s 2014 main report finding, it is that design and IP management has gone well beyond only one system at one site. In fact 82% of companies now have multiple design sites… For the entire system to work, companies will need to have a global design view, while making local AND remote sites EQUALLY efficient.” Drako shares 2014 survey data, requirements for global projects, and 15 features and gotchas to consider when comparing IP and Design Data Management tools.

IP Reuse — Design and Verification Report 2013

This is the fifth annual survey report related to Design and IP Management. It is based on an independent worldwide survey executed during February 2013. A total of 372 engineering professionals responded, with approximately half in management roles. This report focuses closely on IP reuse for design and verification across the enterprise, including both digital and custom/analog design. The report’s scope spans: Non-Memory SoC & IC design percentages of internal IP, 3rd party IP, and new design content; IP reuse and verification, top IP reuse dependency management challenges; percentage of tape outs with known bugs; measured ROI from IP reuse dependency management system; and organizational incentives to increase internal IP reuse.

Global Design Management Report 2012

This report is the fourth annual review of Global Design Management. It is based on an independent worldwide survey executed during April 2012. 524 engineers and engineering managers completed the survey. Its scope spans: trends in design data management driving forces from 2009 to 2012; design management system adoption trends; missing functionality from open source systems; critical features for IP reuse and logistics management; design file management challenges, including broad EDA tool slowdown due to network storage bottlenecks; and drawbacks with using symbolic links. Last year’s survey results showed that designers spend 24% of their time working on design management related tasks. This year’s comprehensive report can help semiconductor companies anticipate the technology drivers and trends and better ensure their design teams collaborate efficiently across the enterprise.

Whitepaper: Best Practices for Maximizing IP Reuse in SoC, IC and FPGA Design

The ability to create differentiated products for SoC, IC, and FPGA designs within narrow market windows depends heavily on how effectively design IP can be reused. This whitepaper covers best practices that can be employed to maximize the efficient reuse of internal and external IP from a data perspective. It discusses core development practices which lay the ground work for quality IP development, along with efficient mechanisms to manage a company’s dynamically changing IP across divergent design teams and derivative designs.

Whitepaper: Unifying Bug Tracking with Design Data Management

IC Design verification continues to take up a majority of the design effort in a project. The effort is further complicated by the fact that design and verifications teams can be composed of many groups dispersed through local and global organizations. It is critical that members of a project be aware of a bug’s existence and status.

A recent poll showed tracking and fixing bugs as the top reason to use Design Data Management. An ideal bug tracking and management system integrates bug tracking within design management with revision control to provide defect traceability to the entire team throughout the design process. This approach will reduce the overall verification effort and help guarantee that bugs do not make their way into the final chip, plus prevent them from appearing in derivative designs

Whitepaper: IC Design Management Best Practices

The paper outlines best practice procedures encompassing:
1. Understanding the design’s organizational structure
2. Partitioning for reuse
3. Organizing according to designer workflow
4. Using branching with history to make changes
5. Doing release management through branching
6. Establishing change propagation policies
7. Making workspace management effective
8. Facilitating frequent updates

Global Design Management Report 2011

This report is the third annual review of Global Design Management. It is based on an independent worldwide survey executed during April 2011.

465 SoC and IC design professionals – both engineers and engineering management – responded to the survey. This report analyzes the survey results and identifies relevant emerging trends. Its scope spans: the increasing important of IP reuse, integration and verification from a design management standpoint; general design data management driving forces; engineering time associated with managing design management tasks; and ROI and adoption of design management systems.

A key goal of the report is to define the critical elements semiconductor company management must address to guarantee that up-to-date design content is immediately available to all design and verification team members across the enterprise.

Whitepaper: Using IC Manage GDP for Collaborative Custom IC (Virtuoso) and Digital SOC Design

This white paper explores the typical components, processes and flows used to create an SOC, as well as the intricacies of collaboration among interdependent design teams. It will also show how IC Manage’s Global Design Platform (GDP) can serve as a foundation for unifying the entire SOC design and verification process, and illustrates how it works for Custom IC Design with Cadence Virtuoso. GDP uses shared workspaces and change-based design methods that efficiently deal with constant changes and propagating those changes as needed for both the initial design and all the derivatives.

Global Design Management Report 2010

This report is the second annual review of the findings of an independent worldwide Global Design Data Management survey. The survey was executed during April and May of 2010 and had 426 IC design professionals respond; we analyze the survey results and identify relevant year to year trends.

The Global Design Data Management report scope includes: general design data management driving forces; the impact on engineering overhead, project deadlines and ROI; adoption of commercial systems; and missing elements of open source revision control.

By analyzing this comprehensive feedback from IC design engineers and engineering management, we can better understand how hardware design data management systems are impacting semiconductor company management’s ability to guarantee that up-to-date design content is immediately available to all design team members. This becomes especially critical with globally dispersed teams working around the clock to meet tight deadlines.

Global Design Management Report 2009

This report is the first annual review of Global Design Management. It is based on an independent worldwide survey executed during April 2009

Highly Scalable, High Performance Perforce Server Environments

Shiv Sikand & Roger March, Matrix Semiconductor, Inc.
May 2003 Perforce Users Conference, Las Vegas, Nevada

High Performance Scalable Hardware Configuration Management

Shiv Sikand, Vice President, Engineering, IC Manage, Inc.
September 2003 International Cadence Users Group Conference

Advanced OpenSource Design Management for 4.4

Shiv Sikand, Silicon Graphics, Inc.
September 2000 International Cadence Users Group Conference, San Jose, California