524 SoC and IC design professionals completed this online survey in April 2012. The top three driving reasons they gave for using a design management system are: easier to trace & fix bugs; easier team collaboration; and IP reuse/logistics management. IP reuse/logistics doubled in importance over the past four years of this survey, while the top two items remained consistent over the same time period. The three most critical features cited for IP reuse/logistics management is bug notification and tracing, integrating and assembling the IP in the design, and efficiently making internal IP available for reuse.
41 percent of organizations have deployed a commercial DM system in 2012. The number of open source systems in 2012 was 44 percent. Top 3 functions missing from open source systems were EDA tool integration, bug dependency tracing across versions, and IP reuse/logistics management, followed closely by advance branching and merging with history.
Designers’ biggest file management problem is that creating and/or updating remote workspaces with many files is slow, followed by application slowdown due to network storage bottlenecks, creating and updating local workspaces with many files is slow, and storage capacity is not keeping up with expanding data volumes.
The design tools impacted by the network storage bottlenecks are broad reaching, and include place and route, functional verification, timing analysis, SPICE simulation and analysis, physical verification and custom Layout. The network storage bottlenecks account for 30% of iteration time for those applications.
Approximately three-quarters of engineers using symlinks cited major issues with it for disk space management. The number one issue for respondents is the lack of control when using mirrors due to automatic data push or out of sync mirrors. This is followed by workspace instability when versions are removed from the network cache to recover space. 28 percent mentioned security problems caused by difficulty managing directory permissions.
About IC Manage
IC Manage provides high performance design and IP management solutions for companies to efficiently collaborate on single and multi-site designs. IC Manage lets designers dynamically track, control and distribute library, block-level and SOC design data, including configurations and properties. Design teams can improve product quality, designer productivity, team collaboration, and bug tracking, plus maximize reuse of existing assets through swift derivations of existing IP. IC Manage is headquartered at Suite 100, 15729 Los Gatos Blvd., Los Gatos, CA. For more information visit us at www.icmanage.com.
Shiv Sikand, Vice President of Engineering, IC Manage
Since co-founding IC Manage in 2003, Shiv has pioneered out-of-the box design data flows for full custom, mixed signal and digital design for more than 50 leading semiconductor companies, allowing them to reduce costs and increase quality and productivity. Shiv first started tackling the problems related to design data management at HAL Computer Systems during the SPARC v9 development program. It was while working on the MIPS processor families at SGI that he designed, implemented and deployed cdsp4, the Cadence-Perforce integration after extensive research. Prior to co-founding IC Manage, Shiv was at Matrix Semiconductor working on the world’s first three-dimensional memory chips. He did his postgraduate research on the design of asynchronous controllers at the University of Manchester, UK in collaboration with ARM Ltd, Philips Research Labs in Holland and IMEC in Belgium. Shiv received his BSc and MSc degrees in Physics and Electrical Engineering from the University of Manchester Institute of Science and Technology.