Global Design Management Report 2011

Shiv Sikand, IC Manage


This report is the third annual review of Global Design Management. It is based on an independent worldwide survey executed during April 2011.

465 SoC and IC design professionals – both engineers and engineering management – responded to the survey. This report analyzes the survey results and identifies relevant emerging trends. Its scope spans: the increasing important of IP reuse, integration and verification from a design management standpoint; general design data management driving forces;  engineering time associated with managing design management tasks; and ROI and adoption of design management systems.

A key goal of the report is to define the critical elements semiconductor company management must address to guarantee that up-to-date design content is immediately available to all design and verification team members across the enterprise.

The topics covered are:

  1. Survey methodology and demographics
  2. SoC/IC design primary bottlenecks
  3. Organizational drivers for deploying design management systems
  4. Top challenges for managing semiconductor IP
  5. Design and verification time associated with design management tasks
  6. Design management systems – Current adoption and 2011 plans
  7. Summary and ROI Impact

I. Survey Methodology and Demographics

A blind, anonymous survey was emailed to several thousand SoC/IC design professionals worldwide by an independent consultancy during April 2011. 465 engineers and managers completed the survey online. The survey respondents included of a broad spectrum of designers and engineering management. The majority of respondents (54%)  held engineering/project management (41%) or CAD management (13%) positions.

DDM Survey2011-1

II. SoC/IC Design Primary Bottlenecks

The primary two areas of SoC/IC design cited as needing the most advancement over the next two years were Electronic Design Automation (EDA) verification tools (63%) and IP collaboration tools (50%).

Following those categories were EDA design tools (42%) and embedded software tools (26%).

DDM Survey2011-2

III. Organizational Drivers for Deploying Design Management Systems

The top drivers for using design data management systems were ease of bug tracking/fixing (56%) and team collaboration (50%). These have ranked as the top two drivers now for all three years of running this survey.

The second tier justifications this year were improved designer efficiency (39%) and better IP reuse (36%). Better IP reuse increased significantly in ranking year over year, having been at 23 percent in 2010.

Other reasons cited were access to prior working configurations (32%) , reduced project delays (29%), better product quality (27%),  and better derivative management (19%).

DDM Survey2011-3

IV. Top Challenges for Managing Semiconductor IP

Given the growing importance placed on managing semiconductor IP, it is vital to identify the challenges faced. Key challenges in managing semiconductor IP are: Verifying IP (62%); Integrating/assembling the IP in the design (53%); Efficiently making internal IP available for reuse (50%); and Managing IP updates and bug fixes (48%).

These challenges were followed by: Finding and selecting optimal IP (39%), and Tracking IP usage (21%).

DDM Survey2011-4

V. Design and Verification Time Associated with Design Management Tasks

Design data management tasks create substantial additional overhead on design teams. Designers now spend an average of 24 percent of their time working on design management related tasks. Over half of respondents (53%) said they spent at least 20% of their time on design management tasks.

DDM Survey2011-5

VI. Design Management Systems – Current Adoption and 2011 Plans

55 percent of respondents stated their organizations have a design management system deployed. Another 21 percent said their organizations intend to evaluate or implement a DM system in 2011, pointing to as much as 38 percent growth in adoption this year.

Design management system deployment has gained major ground in organizations over the last two years since this survey was first run.  Three-quarters (76%) of respondents indicated their organization that had either already deployed a DM system or planned to evaluate or implement one in 2011. This number grew 30 percent over the last two years; the combined number in 2009 was 42 percent.

DDM Survey2011-6

VII. Summary and ROI Impact

Report Highlights:

EDA Verification tools and IP Collaboration tools (IP Selection-Reuse-Integration) ranked as the top two technology areas of SoC/IC design needing advancement over the next two years. Organizational deployment of design management systems is now at 55 percentcompared with 42 percent deployment in 2009. Another 21% of organizations are planning to evaluate or implement them in 2011, pointing to a possible market growth of up to 38 percent in 2011.

The top reasons to use DDM continue to be bug tracking/fixing  and team collaboration, while IP reuse moved up to 36 percent in 2011, increasing from xx% in 2010.

Top challenges in managing semiconductor IP were: Verifying IP; Integrating/assembling the IP in the design; Efficiently making internal IP available for reuse; and Managing IP updates and bug fixes. These challenges were followed by: Finding and selecting optimal IP, and Tracking IP usage.

Designers now spend an average of 24 percent of their time working on design management related tasks.

Return on Investment analysis, updated for 2011 survey findings:

The financial impact resulting from design management issues for a typical 50 person engineering team can be more than $3 million per year. Several factors contribute to this amount:

  • For a 50 person engineering team with a cost of $10M/year, 24% additional overhead (from this survey) on designer’s time associated with design data management issues equates to $2.4 M annually. A commercial DDM that can bring this overhead down to 10% will yield a $1.4 M
  • For the average product delay of approximately 3 weeks (from the 2010 survey), the engineering development cost for a 50 person team would increase by about $600K. If a complete re-spin is involved, it could conservatively add another $500K in costs.
  • For a new product expected to generate $50M in revenue, depending on the length of the product lifecycle, a product delay of 3 weeks could easily reduce product revenue by $1.25M. A commercial design data management system can reduce and even eliminate this delay risk.

On average, a commercial design data management system that can reduce designer overhead associated with manual design data management costs roughly $2.5K per engineer/year, which equates to $125K/year for the same 50 person engineering team.

When we combine the above factors, a representative 50 person organization can expect an annual 20X return on investment from deploying the right Design Management system. It is our view that the right design management system must minimally include the following elements:

  1. Integrated Bug Management
  2. IP Reuse technology
  3. Centralized information exchange for the full SoC/IC flow
  4. Low overhead for design and verification engineers
  5. Configurable Security

Other technical papers:

Using IC Manage GDP for Collaborative Custom IC (Virtuoso) and Digital SOC Design
Global Design Platform Highlights Demo (5 minutes)
IC Design Management Best Practices Whitepaper
Unifying Bug Tracking and Design Data Management Whitepaper

About IC Manage

The IC Manage Global Design Platform (GDP) lets designers track, control, and distribute design, configuration, and IP property data. It enables swift and accurate derivations from existing IP, empowering your team to reuse existing assets.  IC Manage GDP stores and maintains your global organization’s design, stimulus, results, bug tracking and documentation data – spanning digital and custom flows – in one central location. All data that is authorized for sharing is rapidly accessible worldwide and secured by IC Manage ArmorT protection. GDP also includes built-in IT capabilities such as hot backup, high availability, and disaster recovery for 24×7 enterprise availability. For more information, please go to:

Shiv Sikand, Vice President of Engineering, IC Manage

Since co-founding IC Manage in 2003, Shiv has pioneered scalable, multi-site design management software for custom and digital design flows for more than 50 leading semiconductor companies, allowing them to reduce costs and increase quality and productivity. Shiv first started tackling the problems related to design data management at HAL Computer Systems during the SPARC v9 development program. Prior to founding IC Manage, Shiv worked on the MIPS processor families at SGI, and at Matrix Semiconductor working on the world’s first three-dimensional memory chips. He did his postgraduate research on the design of asynchronous controllers at the University of Manchester, UK in collaboration with ARM Ltd, Philips Research Labs in Holland and IMEC in Belgium. Shiv received his BSc and MSc degrees in Physics and Electrical Engineering from the University of Manchester Institute of Science and Technology.