VII. Summary and ROI Impact
EDA Verification tools and IP Collaboration tools (IP Selection-Reuse-Integration) ranked as the top two technology areas of SoC/IC design needing advancement over the next two years. Organizational deployment of design management systems is now at 55 percentcompared with 42 percent deployment in 2009. Another 21% of organizations are planning to evaluate or implement them in 2011, pointing to a possible market growth of up to 38 percent in 2011.
The top reasons to use DDM continue to be bug tracking/fixing and team collaboration, while IP reuse moved up to 36 percent in 2011, increasing from xx% in 2010.
Top challenges in managing semiconductor IP were: Verifying IP; Integrating/assembling the IP in the design; Efficiently making internal IP available for reuse; and Managing IP updates and bug fixes. These challenges were followed by: Finding and selecting optimal IP, and Tracking IP usage.
Designers now spend an average of 24 percent of their time working on design management related tasks.
Return on Investment analysis, updated for 2011 survey findings:
The financial impact resulting from design management issues for a typical 50 person engineering team can be more than $3 million per year. Several factors contribute to this amount:
- For a 50 person engineering team with a cost of $10M/year, 24% additional overhead (from this survey) on designer’s time associated with design data management issues equates to $2.4 M annually. A commercial DDM that can bring this overhead down to 10% will yield a $1.4 M
- For the average product delay of approximately 3 weeks (from the 2010 survey), the engineering development cost for a 50 person team would increase by about $600K. If a complete re-spin is involved, it could conservatively add another $500K in costs.
- For a new product expected to generate $50M in revenue, depending on the length of the product lifecycle, a product delay of 3 weeks could easily reduce product revenue by $1.25M. A commercial design data management system can reduce and even eliminate this delay risk.
On average, a commercial design data management system that can reduce designer overhead associated with manual design data management costs roughly $2.5K per engineer/year, which equates to $125K/year for the same 50 person engineering team.
When we combine the above factors, a representative 50 person organization can expect an annual 20X return on investment from deploying the right Design Management system. It is our view that the right design management system must minimally include the following elements:
- Integrated Bug Management
- IP Reuse technology
- Centralized information exchange for the full SoC/IC flow
- Low overhead for design and verification engineers
- Configurable Security
Other technical papers:
Using IC Manage GDP for Collaborative Custom IC (Virtuoso) and Digital SOC Design
Global Design Platform Highlights Demo (5 minutes)
IC Design Management Best Practices Whitepaper
Unifying Bug Tracking and Design Data Management Whitepaper
About IC Manage
The IC Manage Global Design Platform (GDP) lets designers track, control, and distribute design, configuration, and IP property data. It enables swift and accurate derivations from existing IP, empowering your team to reuse existing assets. IC Manage GDP stores and maintains your global organization’s design, stimulus, results, bug tracking and documentation data – spanning digital and custom flows – in one central location. All data that is authorized for sharing is rapidly accessible worldwide and secured by IC Manage ArmorT protection. GDP also includes built-in IT capabilities such as hot backup, high availability, and disaster recovery for 24×7 enterprise availability. For more information, please go to: www.icmanage.com.
Shiv Sikand, Vice President of Engineering, IC Manage
Since co-founding IC Manage in 2003, Shiv has pioneered scalable, multi-site design management software for custom and digital design flows for more than 50 leading semiconductor companies, allowing them to reduce costs and increase quality and productivity. Shiv first started tackling the problems related to design data management at HAL Computer Systems during the SPARC v9 development program. Prior to founding IC Manage, Shiv worked on the MIPS processor families at SGI, and at Matrix Semiconductor working on the world’s first three-dimensional memory chips. He did his postgraduate research on the design of asynchronous controllers at the University of Manchester, UK in collaboration with ARM Ltd, Philips Research Labs in Holland and IMEC in Belgium. Shiv received his BSc and MSc degrees in Physics and Electrical Engineering from the University of Manchester Institute of Science and Technology.