VIII. Summary and ROI Impact – Updated for 2010
Deployment of hardware design data management systems can be expected to grow by 27% in 2010. 47% of engineering, project and CAD managers indicated that design data management issues have caused design and tapeout delays; this results in increased engineering costs and reduced product revenue.
The financial impact resulting from design management issues for a typical 50 person engineering team can be more than $2 million per year. Several factors contribute to this amount:
- For a 50 person engineering team with a cost of $10M/year, 14% additional overhead on designer’s time associated with design data management issues equates to $1.4M annually. A commercial DDM that can bring this overhead down to 4% will yield a $1M savings.
- For the average product delay of approximately 3 weeks, the engineering development cost for a 50 person team would increase by about $600K. If a complete re-spin is involved, it could conservatively add another $500K in costs.
- For a new product expected to generate $50M in revenue, depending on the length of the product lifecycle, a product delay of 3 weeks could easily reduce product revenue by $1.25M. A commercial design data management system can reduce and even eliminate this delay risk.
On average, a commercial design data management system that can reduce designer overhead associated with manual design data management costs roughly $2.5K per engineer/year. This equates to $125K/year for the same 50 person engineering team. The representative 50 person organization can expect an annual 15X return on investment from deploying a Design Management system.
In addition to reducing or eliminating version and configuration errors, other primary functions of an IC Design Management system are to: reduce the time it takes to find, track and fix development bugs; increase design team collaboration; improve designer efficiency; raise product quality, and improve IP reuse. To achieve a 15x ROI for design groups, these systems must focus on easy of deployment, minimal set up time, and integration in EDA tool flows.
About IC Manage
IC Manage, Inc. provides a high performance, scalable, reliable design management system, for managing IC design data across global design teams. IC Manage Global Design Platform (GDP) is a comprehensive set of tools and configurable workflows to improve product quality, designer productivity, team collaboration, bug tracking, and IP reuse and management of derivative designs. GDP also includes built-in IT capabilities such as hot backup, high availability, and disaster recovery for 24×7 enterprise availability. For more information, please go to: www.icmanage.com.
Shiv Sikand, Vice President of Engineering, IC Manage
Since co-founding IC Manage in 2003, Shiv has pioneered out-of-the box data flows for full custom, mixed signal and digital design for more than 50 leading semiconductor companies, allowing them to reduce costs and increase quality and productivity.
Shiv first started tackling the problems related to design data management at HAL Computer Systems during the SPARC v9 development program. It was while working on the MIPS processor families at SGI that he designed, implemented and deployed cdsp4, the Cadence-Perforce integration after extensive research. Prior to founding IC Manage, Shiv was at Matrix Semiconductor working on the world’s first three-dimensional memory chips. He did his post-graduate research on the design of asynchronous controllers at the University of Manchester, UK in collaboration with ARM Ltd, Philips Research Labs in Holland and IMEC in Belgium. Shiv received his BSc and MSc degrees in Physics and Electrical Engineering from the University of Manchester Institute of Science and Technology.