AMD – Design and IP Management Best Practices

Vincent Ross, AMD (DAC Panel 2012 edited transcript)

The top two challenges addressed by AMD design management systems.

Essentially, supporting multiple parallel product tape outs and IP reuse. AMD does many parallel ASICs, taping out at multiple sites throughout the world. Making sure we had the right version of the IP going out on the right version of the parallel products, all in tapeout, is incredibly important. We effectively need to do this to minimize cost.

Also, alignment of these multi-site teams.  It is quite easy to get unsynchronized when you’ve got a very diverse engineering organization.  Getting clarity on things like the design requirements, the ability to change the design requirements, and staying synchronized across all those design sites. Being able to make sure we have consistent design against the right version of the technology inputs. Making sure all the various sites and design organizations are handing off their deliverables to the same associated sets and quality standards. Ensuring that the correct version of the sanity check points are being run at the correct points in the design cycle, and having the ability of a design system to effectively take learning from history and upgrade the overall system.

In terms of best practices from a design and IP management system – essentially specification-driven IP design, change control, and that sort of thing – we need to ensure that we have the correct views ready for handoff, including all the nitty gritty things like the appropriate PVT lists, etc. that a given SoC product would need.

Leveraging revision control. There are really 2 levels of revision control we need to worry about. One is what I call coarse grained – essentially, the hand-off of large IP blocks to the various SOCs, and making sure that the correct version of an IP block makes it to tape out. There is also a finer grain characteristic, that is more in tune with the development of the sub-IP itself.

Enabling things like schematic layout to be co-designed at different design sites. Being able to bring in contractors, leveraging all those coordination issues, really needs a very good and robust fine grained schematic and layout revision control type of system.

AMD is leveraging IC Manage, definitely, for this aspect of that workflow.

Quick rework and turnaround times. We need the ability to be able to react to unforeseen changes. Whether it be changes in the technology very close to tape out, or feedback from the SOC integration organizations that needs to be reworked into the sub-IP before getting ready for the final push.

In terms of ‘must haves’ – we talked quite a bit internally about this. One of the big challenges we see is US export control.

That has turned out to be an incredibly important thing to get a handle around. So having the design system be compliant to the regulatory restrictions, having that percolate across the multiple design databases, and correct controls, as per what Doug (Doug Quist, Nvidia) was alluding to. Basically, only if you need to know the design data to work with it, should you have access to that data.

Efficient large data set synchronization across sites. Transfer speeds, smart caches, all are needed to ensure that you’ve got multi-site design organizations enabled and that their costs are controlled.

Another aspect is waiver enablement and control. To a large degree this talks to agility. There are occasions when waivers are needed to ensure that the right engineering and management judgments can be put into place to ensure that the tapeouts can still be achieved on time.

Integration of test  regression and connectivity to the design management databases. The ability to see percentage of test coverage, various aspects of IP status, are also important to understand through the various phases of the ASIC development, especially for management. So, some of the outcomes of implementing some of the best practices and must-haves.

Effectively enabling AMD to be able to tape out multiple parallel products per year and per business unit. We have the challenge of IPs going into many possible parallel ASICs. That all has to be tracked and the correct versioning understood, as well as tape-out organizations all pushing that work in parallel, means that it’s very easy to get defocused on any one specific IP.

Enabling a world wide engineering organization. Again, making sure that everyone is aligned to the definitions and the proper frameworks is incredibly important to minimize mishaps. And the ability, to to react quickly to unforeseen conditions, including late fab techfiles.

In terms of a quantification, we have a very hard time clearly defining the quantifiable benefit from a specific design management implementation. Primarily because the ASIC complexity is growing every single year as well, as the complexity of the foundry technologies that we happen to be using. So the best way of saying it is the capability to still tape out these very large and ambitious products is a testament to the design management system in itself.


Vincent Ross is a CAD architect at AMD